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On how to efficiently exploit reconfiguration aspects from your design - The FASTER tool chain

Extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customer’s needs and market and technology trends. While adaptability of software components is straightforward, products include hardware accelerators –for reasons of performance and power efficiency- that also need to adapt to the new requirements. Hardware solutions can achieve high performance, and software solutions can easily adapt to the new set of threats, but neither can achieve flexibility and high performance at the same time. Reconfigurable logic allows the definition of new functions to be defined in hardware units, combining hardware speed and efficiency, with ability to adapt and cope in a cost effective way with expanding functionality, changing environmental requirements, improvements in system features, changing protocols and data-coding standards, etc. However, designing, implementing and verifying reconfigurable hardware systems is harder compared to static ones. This workshop aims at bringing together experts to discuss current technologies and trends in the reconfigurable computing area. This tutorial tends to focus on different topics/objectives of the design of computing systems to include reconfigurability as an explicit design concept. Current tools seem to lack a framework for system design where run-time adaptability, provided by dynamic hardware reconfiguration, becomes pivotal to computing system design. In this tutorial we will present cutting-edge research aiming at developing techniques and tools that analyze the structure and performance of the application, map it according to the capabilities of the underlying implementation platform, and provide a dynamically reconfigurable system implementation, e.g. through both micro-reconfiguration and module-based reconfiguration.


  • "An overview on the tutorial and on the FASTER tool chain", Marco D. Santambrogio, Politecnico di Milano [1.30pm - 2pm]
  • "Optimization of applications for micro-reconfigurable core implementation", Dirk Stroobandt, Univeristy of Ghent [2pm – 3pm]
  • "Application task profiling and identification of reconfigurable cores", Riccardo Cattaneo, Politecnico di Milano [3pm – 3.30pm]
  • Coffee Break 3.30pm – 4.00pm
  • "Application task profiling and identification of reconfigurable cores. Hands-on experience on the private FASTER VM", Riccardo Cattaneo, Politecnico di Milano [4pm – 5pm]
  • "Compile-time baseline scheduling and core mapping onto reconfigurable regions. Hands-on experience on the online public available FASTER VM", Marco Rabozzi, Politecnico di Milano [4pm - 5pm]